STM NAND512R3A boot problem: RBL&UBL&ECC
dal_loma at yahoo.com
Tue Aug 28 23:40:41 CDT 2007
Long back guys here faced the similar problems with
the NOR booting - with CCS it's fine, without CCS, it
does not boot. They fixed it by changing Os to O2 for
Here, ubl is also in picture along with RBL.
Also, read Appendix D, "Supported NAND Devices" in
. Not sure if it is related to what you are facing
--- Vitaly Makarov <vit.macarrow at gmail.com> wrote:
> Hi Amol,
> This issue happens when there is no software in the
> system except for
> RBL. And if I cause the delay to the DaVinci ARM or
> whatever else
> happens when JTAG starts and stops it RBL can boot
> the UBL which
> means for me that there is no issue with writing to
> the flash or
> calculation of ECC.
> But anyway thank you, I will try :-)
> On Aug 28, 2007, at 9:18 PM, Amol Lad wrote:
> > Try removing -Os from ubl/src/makefile.
> > --- Vitaly Makarov <vit.macarrow at gmail.com> wrote:
> >> Ivan,
> >> As another test I run the new board connected
> >> JTAG to the CSS and
> >> tried to debug the RBL. And got wierd results:
> >> if I do step-by-step execution for the code in
> >> memory from address
> >> 0x4000 to address 0x403C allowing about 5 seconds
> >> per step and make it
> >> free run from the address 0x43C board _will boot_
> >> ubl and u-boot.
> >> Vitaly
> >> Ivan Tonchev wrote:
> >>> Hi Vitaly,
> >>>> Talking about delay that is weird if RBL tries
> >> fix the ECC errors
> >>>> because the flash is empty and filled with 0xFF
> >> as I can see it from
> >>>> the u-boot.
> >>> I misunderstood you. I thought that on the STM
> >> board, when the flash
> >>> was empty, you saw no delay. But obviously you
> >> were talking about the
> >>> Samsung board. Sorry, my bad :)
> >>> You can ask TI people to provide you with RBL
> >> source code or debug the
> >>> RBL disassembly with CCS.
> >>> BR,
> >>> Ivan
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