Confusion about CLE and ALE on the emif
James T Long
j-long7 at raytheon.com
Wed Sep 3 11:19:36 CDT 2008
Would someone please clear up the following for me?
The documentation for the the EMIF (srue20b) and the source code for
DVFlasher both say :
To talk to NAND-Flashes:
Tie A to CLE and A to ALE. Apparently A and BA[1:0] are not
to set CLE low and ALE low, then use offset 00h
to set CLE high and ALE low, then use offset 10h
to set CLE low and ALE high, then use offset 0Bh
Why 0B? If it's something to do with Endian-ess (to align the
command/address to the nand, perhaps), then
why not offsets (in order) 03h, 13h and 0Bh?
Obviously 0Bh is okay, since the code works, but I don't understand the
emphasis on '0B'.
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